Analog-to-digital converters (ADCs) are employed in a variety of electronic systems including computer modems, wireless telephones, satellite receivers, process control systems, etc. Such systems demand cost-effective ADCs that can efficiently convert an analog input signal to a digital output signal over a wide range of frequencies and signal magnitudes with minimal noise and distortion.
An ADC typically converts an analog signal to a digital signal by sampling the analog signal at pre-determined sampling intervals and generating a sequence of binary numbers via a quantizer, wherein the sequence of binary numbers is a digital representation of the sampled analog signal. Some of the commonly used types of ADCs include integrating ADCs, Flash ADCs, pipelined ADCs, successive approximation register ADCs, Delta-Sigma (ΔΣ) ADCs, two-step ADCs, etc. Of these various types, the pipelined ADCs and the ΔΣ ADCs are particularly popular in applications requiring higher resolutions.
A pipelined ADC circuit samples an analog input signal using a sample-and-hold circuit to hold the input signal steady and a first stage flash ADC to quantize the input signal. The first stage flash ADC then feeds the quantized signal to a digital-to-analog converter (DAC). The pipelined ADC circuit subtracts the output of the DAC from the analog input signal to get a residue signal of the first stage. The first stage of the pipelined ADC circuit generates the most significant bit (MSB) of the digital output signal. The residue signal of the first stage is gained up by a factor and fed to the next stage. Subsequently, the next stage of the pipelined ADC circuit further quantizes the residue signal to generate further bits of the digital output signal.
On the other hand, a ΔΣ ADC employs over-sampling, noise-shaping, digital filtering and digital decimation techniques to provide high resolution analog-to-digital conversion. One popular design of a ΔΣ ADC is multi-stage noise shaping (MASH) ΔΣ ADC. A MASH ΔΣ ADC is based on cascading multiple first-order or second-order ΔΣ ADCs to realize high-order noise shaping. An implementation of a MASH ΔΣ ADC is well known to those of ordinary skill in the art. While both pipelined ADCs and ΔΣ ADCs provide improved signal-to-noise ratio, improved stability, etc., ΔΣ ADCs generally provide higher levels of resolution and therefore are preferred in applications involving asynchronous digital subscriber lines (ADSL), very high speed digital subscriber lines (VDSL), etc. Highly-linear, high-resolution and wide-bandwidth ADCs are required for VDSL systems.
Any stage of a pipelined ADC can be calibrated digitally by inserting a pseudo-random test signal at an input of the stage to be calibrated. However, adding such pseudo-random test signal at one stage may result in such an output signal from the calibrated stage that the stage following the calibrated stage may be saturated. Thus for example, if a first stage of a pipelined ADC is calibrated using a pseudo-random test signal, the second stage of the pipelined ADC will be saturated.